1. Field of the Invention
The present invention relates to an integrated circuit structure built on a substrate wafer manufactured from a larger semiconductor crystal, for the purpose of undertaking a quality check of the wafer material. In particular, the structure encompasses field effect transistors, interconnecting conductors and pads.
2. Description of the Prior Art
Circuit elements and technology for testing certain types of integrated circuits are described, for example, in "Electronic Engineering," Vol. 54, No. 663, March 1982 at pages 53-57. General teachings regarding integrated circuit examples are provided therein, for example, gate arrays, master slices, and logic arrays. The structures and techniques described in this article are directed to designing the interconnection of the individual semiconductor functional elements forming an array. Details regarding line management of such integrated circuits to be employed in practice are also described.
An introduction to ultra-fast 8000-gate CMOS gate arrays is provided in "The 2nd International Conference on Semi-Custom ICs," November 1982, at pages 1-7. LSI circuits are also discussed in this publication, particularily techniques for realizing such circuits on semiconductor chips of corresponding size. As described in this publication, it is important that the material of a semiconductor chip carrying the LSI circuit have uniformity and freedom from defects such that every individual functional element of the integrated circuit is operational. The outage of even a single function can make the entire integrated circuit or the entire semiconductor chip worthless.
For this reason, it is standard practice to check substrate wafers, which are to be employed for semiconductor circuits, for their operability and freedom from defects before undertaking manufacture of the actual semiconductor chips. The substrate wafers which are tested is a relatively large diameter, but extremely thin, wafer. Such wafers may have a diameter of up to a few inches and are produced from a grown semiconductor crystal such as, for example, by sawing. Such a semiconductor crystal is divided into such substrate wafers by a plurality of parallel saw cuts. The quality check is usually executed in the form of spot checks. It has been shown that the result of the quality check of one substrate wafer provides valid evidence for the quality of substrate wafers produced in the proximate region from the same crystal.
A known method for performing such a quality check is to produce a structure on the substrate surface specifically for this purpose, the structure comprising field effect transistor structures in a grid spacing of approximately 200 .mu.m, which are immediately surrounded by the terminal pads. The source/drain region of one transistor also functions as the source/drain region of the neighboring transistor, so that only one terminal pad for both source/drain regions need be present in the lateral direction between two neighboring gate regions. This is advantageous because the terminal pad is relatively large in area. The full surface of a single substrate wafer is covered with such a structure, and thus the entirety of the wafer surface is checked using the specified grid dimension. Conclusions regarding a greater number of substrate wafers cut in proximate fashion from the same crystal can then be drawn from the substrate wafer which was checked. A smaller excerpted region having such a structure can be checked on a substrate wafer with respect to quality, this excerpted region (as the individual substrate wafer described above) is then no longer available for production of integrated circuits, and is discarded.
The result of the quality check achieved with the grid dimension as described above and for variations thereof is relatively satisfactory, particularily if the semiconductor material is silicon. A more sophisticated quality check is required, however, for III-V semiconductor material (gallium arsenide, gallium phosphide, indium phosphide and the like, as well as ternary and quaternary semiconductor material such as gallium aluminum arsenide, gallium arsenide phosphide and the like). It is known that for binary, ternary and quaternary III-V semiconductor materials, a 200 .mu.m grid is inadequate to discover many quality defects with sufficient reliability. The assumption that the quality, or lack thereof, of a tested substrate wafer will be the same for other substrate wafers cut from the proximate region of the same crystal is, however, still valid.